multi_clk_design:

1. Design has three modules in UT level, Transmit sends data from the array in 
   an autonmous thread, interface receives data and passes it on to the display
   block.
   
        clock 1 in FS        clock 2 in PS        clock 3 in NS
              |                    |                    |
         _____V_____          _____V_____          _____V_____
        |           |        |           |        |           |
        | Transmit  |--------| Interface |--------|  Display  | 
        |___________|        |___________|        |___________|
        
 
2. Interface block has two threads, one a slave thread sensitive to input and 
   one clock sensitive thread. Input sensitive thread notify an event ( event
   scheduling ) for every input, the clock sensitve thread wait to receive event
   notification to transfer data to the display block. 
   
3. Threads in all the three blocks are driven by different clocks.
   
   Also, the time is represented in the new notaion of sc_time. The data is 
   transmitted at each clock edge, which has a period of 5 time units, and a 
   duty cycle of 0.5, and start-offset of zero. Each clock-edge generates a 
   new data, and hence an event notification. At the end of the delta delay, 
   the second event gets triggered. The value of the second event occurs at 
   the display at the next clock edge. 

